The present invention relates to generating a current source model of a gate.
Advancement in semiconductor technology has resulted in need for nanometer cell characterization and model generation. Nanometer cell characterization requires complex and efficient models with better timing and noise accuracy. One of the conventional techniques for assessing the speed at which a digital chip runs and determining the signal delay includes static timing analysis.
Determination of the signal delay through a cell is critical for accurate static timing analysis of the digital chip. This is because the output voltage curve is dominated by transistors' non-linear characteristics. Inaccurate determination of the signal delay results in timing closure loops and incorrect analysis.
Several methods have been conventionally used for determining the signal delay of the output signal curve of the digital chip. One such method is based on an instance-based delay calculation. The signal delay calculation is performed by using a timing library. The 2-d data in the timing library is generated, based on a load capacitance and an input signal slew rate, to derive a change in the output voltage with respect to a change in the input voltage. However, this method does not account for the effect of non-linear input transition waveform and complex load.
This problem of circuit level and device-level non-linear characteristics is addressed by another conventionally used method for determining the signal delay. The method determines the signal delay by modeling a cell's output drive as a current source rather than a voltage source. However, this method is capable of only describing the response on the gate for a load that has small resistive shielding and is decoupled.
In light of the foregoing discussion, a need exists for a manner for generating a current source model of a gate, which is capable of computing the output response for arbitrary coupled loads. The present invention addresses such a need.